Static random access memories (“SRAM”) include a plurality of cells disposed in rows and columns to form an array. Conventional SRAM cells include a plurality of transistors coupled to bit lines and word lines that are used to read and write a bit of data to the memory cell. As the size of SRAM cells continues to decrease, the supply voltage VCC is typically lowered to reduce the power consumption of the devices. Lowering the supply voltage reduces the amount of read current, which results in the leakage current being larger relative to the read current. This increase in the leakage current compared to the read current results in difficulty in accurately reading data from the memory cell as well as reducing the speed at which data may be read from or written to the bit cell.